On 02/08/14 22:31, Howard Chu wrote:
Hallvard Breien Furuseth wrote:
> What matters is that nothing *sees* the metapage before its data
> pages, nor sees the mti_txnid change before the metapage. I thought
> that's what cache coherency and memory ordering was about.
No, memory ordering is about seeing partial changes to a single page,
outside of the order that the program wrote it. Which can happen on
superscalar chips with out-of-order execution.
OK, that explains half of that code, thanks:-)
> So to explain my previous message a bit: A cacheflush() which
> a metapage and its datapages all in one chunk makes me nervous. If
> that's necessary (rather than just flushing the meta at that point), I
> imagine that just before the flush, it's possible for something to see
> the metapage before its datapages.
Not possible. The cacheflush is atomic.
Fine, but it's the situation before the flush which worries
me, when the cache can be incoherent.
Note that this is invalidating
an on-chip data cache which is typically only 32KB or so. It has nothing
to do with flushing the buffer cache. ("flush" is a misnomer, but that's
what the syscall is called.)
OK, but apparently it's still a cache which can include
data from both metapages and datapages.
Or is this only relevant for the same thread, and not other
threads/processes (read-only txns starting before the flush)?
In that case it would be safe.