Martin Lucina wrote:
That still doesn't explain the MIPS issues, any suggestions on how to proceed there? I can give someone access to a MIPS host if that would help.
Copying back to the list:
Martin Lucina wrote:
hyc@symas.com said:
It appears that this system also lacks a coherent FS cache, like some BSDs. I changed mtest.c to use MDB_WRITEMAP and it now runs fine.
The unmodified mtest.c also worked when single-stepping thru gdb, which apparently gives time for the cache to sort itself out between mdb function calls.
Interesting. What you're saying is that without MDB_WRITEMAP pages are written out separately and it is up to the FS cache to ensure that reading back via the memory map is consistent, correct?
That's the general idea. As the LMDB design paper states, LMDB requires the OS to use a unified buffer cache - so that mmap pages and FS cache pages are the same.
I'll try and dig through the OpenWRT kernel configuration, they must have changed something that triggers this behaviour.
Frankly it seems unlikely that they could have changed something so fundamental to the VM subsystem of the kernel. It's also possible that we're seeing *CPU* cache inconsistencies, and that adding a few MIPS-specific memory barrier instructions here and there may fix things up.
Unfortunately I need (or will be very unhappy without) nested transactions so I'm going to try and get it working without MDB_WRITEMAP if possible.